library verilog;
use verilog.vl_types.all;
entity MUX_2to1x4 is
    port(
        select_line     : in     vl_logic;
        input_A         : in     vl_logic_vector(3 downto 0);
        input_B         : in     vl_logic_vector(3 downto 0);
        output_mux      : out    vl_logic_vector(3 downto 0)
    );
end MUX_2to1x4;
